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How EDA workloads inside the cloud reinvigorate chip design


The semiconductor industry’s journey to the cloud is now reaching the next destination: IC design companies choosing to host their EDA workloads in the cloud. Cadence’s announcement about the OnCloud SaaS and e-commerce platform powered by Amazon Web Services (AWS) is the latest reminder of a major shift in which semiconductor design is steadily moving beyond traditional enterprise-wide EDA licensing models.

These EDA workflows include front-end design as well as performance simulation and verification, along with backend workloads that include timing and power analysis, design rule checks, and other applications to prepare a chip for production.

Traditionally, semiconductor companies have been running the highly-iterative design workflows from on-premises data centers with fixed compute capacity. However, the increasing complexity of chip designs meant that producing a new semiconductor device could take many months or even years unless semiconductor firms accurately forecast and install additional compute infrastructure.

At the same time, however, chip design engineers forecasting compute requirements often underestimate the compute and EDA resources they need while they experience a growing system complexity in IC designs. So, chip development teams began leveraging a “bring your own cloud” (BYOC) approach offered by EDA vendors. Here, engineers are required to source compute infrastructure from public cloud service providers and are frequently constrained by the pre-defined design and verification capacity.

Figure 1 Hybrid cloud environments provide design engineers with access to pre-installed tools. Source: Synopsys

As a next logical step, EDA vendors started working closely with cloud service providers to transform the landscape through a software-as-a-service (SaaS) on cloud computing platforms like AWS and Microsoft Azure. Cadence teaming up with AWS and Synopsys joining hands with Microsoft Azure mark that stage in the cloud-based EDA movement.

Figure 2 Engineers can directly access and pay any cloud-related design and verification tool with a SaaS platform. Source: Synopsys

At this technology crossroads, while EDA suppliers like Cadence and Synopsys will manage software installation, upgrades and licensing, semiconductor design firms don’t need to procure expensive desktop computing machines, monitor license usage, and maintain data storage systems. Therefore, no time is spent on installation, and engineers can stay focused on completing critical, revenue-generating design projects.

Next, it eliminates the need for costly on-premises compute and server resources that require high levels of maintenance and operational overhead and consume high levels of power. More importantly, by moving its EDA workflows to the cloud, semiconductor companies gain the scale and can run dozens of performance simulations in parallel to accelerate the time to result.

In short, the access to optimized compute and EDA tools in the cloud is an important way forward for an industry grappling with exploding computational demands and continued time-to-market pressure. And it holds for both large semiconductor firms as well as small startups.

Chipmakers joining the fray

Chip designs undergo extensive testing and validation through the EDA process before being sent to the foundry for production. So, semiconductor firms are also moving tasks such as testing and analyzing their designs from on-premises environments to cloud platforms that are purpose-built for EDA workloads.

Case in point: NXP Semiconductors is migrating its EDA workloads from the data centers scattered across multiple locations to AWS to reduce costs with elastic scaling of compute resources and minimize scheduling risks for design projects. So that its engineers could gain more time to focus on actual design work rather than managing compute resources. NXP is using Amazon FSx for Lustre—a cloud service that provides scalable storage for compute workloads like EDA—to store petabytes of design simulation data and make it quickly available for analysis.

Figure 3 This is what a design platform of NXP looks like inside the AWS cloud. Source: Amazon Web Services

The Dutch chipmaker is also using AWS analytics and machine learning services to continuously refine its design workflows. Take Amazon SageMaker—a cloud service that helps developers and data scientists build, train, and deploy machine learning models quickly in the cloud and at the edge—which NXP is using to optimize how it structures compute, storage, and third-party software application licenses.

Then there is Dialog Semiconductor, now part of Renesas, which has been testing and analyzing its chip designs on Oracle’s cloud infrastructure. That allows Dialog engineers to run applications needing multiple workloads and data types in a single converged database.

Journey to the cloud

Massive compute power is involved in IC design cycles, so access to optimized compute and EDA tools inside the cloud will inevitably accelerate the completion of specific functions such as simulation, signoff, and library characterization. Some chip design consultants claim that the cloud-based approach can offer up to 10x run-time improvements compared with traditional on-premises environments.

The new EDA deployment model also delivers new levels of chip and system design flexibility via a single-source, pay-as-you-go approach. It allows design engineers to directly access and pay as they go for cloud compute resources. At the same time, it bypasses the need for on-premise data center investments and further streamlines the EDA workflows.

The recent announcements from Cadence and Synopsys are a harbinger of more cloud-based offerings for semiconductor and electronic system design. Stay tuned for more news about design inside the cloud.

Majeed Ahmad, editor-in-chief of EDN and Planet Analog, has covered the electronics design industry for more than two decades.

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