An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
And yet, every semiconductor project group deals with inefficiencies that constrain them from delivering ideal solutions and limits productivity. Today’s CAD engineers use a patchwork of tools, flows and scripts consisting of commercial electronic design automation (EDA) products, commercial or in-house customized add-ons and in-house intellectual property (IP), a problem for many project groups because of:
- Tool flow gaps in existing EDA products
- The burden of maintaining in-house or homegrown tools, flows and scripts
- The lack of time to build and test high-quality, robust internal tools
That inevitably leads to a bunch of problems, as explained in the following sections.
Endless script design loops
The burden of maintaining in-house or homegrown tools, flows and scripts is one of cascading interventions. It may start out with a design engineer writing a Perl or Tcl script to overcome a roadblock in the design verification process.
As the project group uses it, special cases and functions don’t work. The script gets another rework to refine it and gets passed up to the chip lead for review who notes enhanced automation, then notices that the script does not handle something critical.
More issues arise as more of the project group uses the script. The script gets passed to the internal CAD group for ongoing support and maintenance. More issues arise as the internal CAD department starts to use it. CAD spends three weeks working on the script to address these issues and ongoing maintenance requires one day per week.
It’s not long before support and maintenance of one internal script costs between $50,000 and $100,000 per year. In the end, the script was required for the development process, but the financial and project time cost is high and unpredictable.
The burden of maintenance includes ensuring existing internal tools and flows continue to work. Other maintenance choirs could be adding features to existing internal tools and flows, and shifting to a new hardware description language (HDL), such as Verilog to SystemVerilog, or adding support for an additional HDL due to third-party IP. The estimated cost of updating just one in-house Perl or Tcl script to support SystemVerilog can be $175,000 and six months of project time.
Time is the enemy
A company’s primary goal is to get the silicon device to market fast. The CAD department’s job is to support the designers and verification engineers, which means continuing to prop up the patchwork of tools, flows and scripts hybridized from commercial EDA products and in-house IP.
The lack of time to build robust tools is a problem. A CAD engineer knows what he or she wants a tool to do, knows how to design, implement and test it, but doesn’t have the time to do it.
Homegrown fixes include:
- Turning to open-source parser projects, though they never have the full language coverage or support for new constructs.
- Rewriting internal flows and scripts and using more robust software engineering methodologies, a difficult task to justify the resources to “re-do” work.
- Switching from Perl or Tcl to Python for better understandability and functionality. This does not resolve HDL complexity—the SystemVerilog language reference manual (LRM) is 1,300 pages of complex specifications.
- Jury-rigging existing commercial EDA tools to perform tasks they weren’t meant to do often ends up with unsatisfactory results and a dependency on expensive licenses.
At the same time, the project group is taking a huge risk if CAD is unable to consistently deliver best-in-class design and verification flows. Missing market windows and/or delivering silicon that is not competitive can be fatal to a semiconductor company given the new product cycles and high costs of IC development.
Solutions exist and range from in-house development of custom tools to purchasing a customized tool built by an EDA company, with variations in between.
Four ways to build best-in-class CAD flows
Creating robust, high-performance CAD tools in-house would yield a license-free, proprietary tool that could be the secret weapon to reliably get a chip to market first. It would require building a parser from scratch to detach from any licensing agreements.
- It can be extremely time consuming.
- It requires a deep understanding of HDL languages and how they are used.
- Results may not be robust because the underlying infrastructure is weak and untested.
- The tool may have inadequate testing, leading to an iterative support model.
- It may not track new developments in HDL languages.
- Deployment time could be long, ranging from one year to several years.
License a C++ parser library and hire a software development group to build custom CAD tools that bypass current limitations. This solution is an outsourced variation of the previous one. Commercially available parsers offer benefits, including full-language coverage for VHDL, Verilog, SystemVerilog and UPF.
Internal CAD groups are often more experienced in scripting style languages such as Perl, Tcl and Python and may not have the depth of development expertise in C++. The C++ library can be difficult to use without extensive C++ software development expertise.
Ask an EDA vendor to custom build features/function needed to enable a design flow. An advantage of this solution would be support and maintenance of the requested capability if it’s integrated into the mainline of the product. A consulting project by the EDA vendor would mean the responsibility for additional ongoing consulting services to maintain the feature/function.
What’s more, the company would be beholden to the EDA vendor’s schedule or the vendor may not build or be able to build the customization. The EDA vendor may require upfront payment for non-recoverable engineering (NRE) costs and, if the EDA vendor adds requests to its next release, a customized feature or function becomes available to competitors. Additionally, if the EDA vendor builds a customized tool, there will be ongoing obligations for IP issues and licensing requirements.
In addition, depending on the nature of the project and engagement, the EDA vendor may provide the requested functionality to its other customers, thereby losing any competitive advantage associated with the features/function. Many EDA vendors also provide application engineering support for customizing their tool integration into their customers’ flows. Because this type of expertise is typically provided to other major licensees, it’s not likely to impart a competitive advantage.
License a CAD tool development platform that contains built-in HDL parsers, industrial-quality databases and support for standard file formats for in-house development using mainstream scripting environments. A platform solution like this is intended for design, verification and CAD engineers to quickly create targeted custom applications for semiconductor design and verification.
A robust, high-performing and easy-to-use CAD tool development platform should:
- Provide complete parsing of Verilog, SystemVerilog, Verilog-AMS, VHDL, Liberty and UPF.
- An intuitive API with a language familiar to a hardware engineer such as Python that abstracts complexity and enables specific control when needed.
- Be pre-tested on a large set of benchmarks that prove typical use cases and all of the HDL language behaviors, including constructs and use cases.
- A support model that describes using the tool and access to consulting services to supplement development.
- Fully operational sample applications easily modified for a user’s specific case.
CAD tool development platform
The biggest challenge that internal groups face is gaining access to robust, easy-to-use and maintain and continually supported HDL parsing environments. A CAD tool development platform providing both ease of use and robust capabilities would free the group from the limits of commercial EDA flows while offering capabilities to differentiate its design flow. Additional benefits are cost savings on EDA tool licenses, time savings in CAD tools, flow and script development and increased productivity for design, verification and CAD engineers.
The CAD tool development platform would require an upfront investment, rather than making use of free scripting tools like Perl and Tcl, a drawback that needs to be considered. With the move from Verilog to SystemVerilog, for example, simple Perl or Tcl scripts are not feasible due to the additional complexities of the language. A CAD tool development platform designed for HDL exploration and modification will enable new and innovative tools and flows not possible using general-purpose text-parsing capabilities.
A CAD tool development platform is an investment that allows fully utilized human capital; valuable R&D resources thinking about building the best ICs, not fighting to debug ad hoc Perl scripts.
Another drawback is the question of robustness of the parsing capability for SystemVerilog, VHDL or UPF. To be successful, the platform must be based on a widely used and tested HDL parser library. Without it, each new design or project will reveal more limitations of the parser. Only parsers actively used by thousands of engineers and actively maintained can handle arbitrary new designs.
Closing gaps in a CAD flow and getting off the endless cycle of script design and debug, a licensed CAD tool development platform provides the capability to leverage commercial-grade HDL parsers while simplifying their use.
Daniel Hoggar is a senior member of technical staff at Verific Design Automation.