British photonic computing startup Salience Labs has raised an $11.5 million seed round to develop its hybrid photonic-electronic chip, which will eventually target AI inference acceleration in applications that need low latency. This includes robotics, vision systems, healthcare and many other applications.
Salience, a spin-out from the Universities of Oxford and Münster which was established in 2021, is targeting an order of magnitude increase in performance versus today’s electronic chips with its first product.
The concept of photonic computing is not new, but the supporting technologies required are only just coming together, Salience Labs co-founder and CEO Vaysh Kewada told EE Times.
“The reason that we think it’s possible today is that the manufacturing process has come leaps and bounds in the last five to seven years,” she said. “It’s now possible to go and fabricate a photonic chip using CMOS processes at a production level foundry; you can go tomorrow and tape out a photonic chip. The development of this manufacturing process was essentially predicated on the development of optical transceivers, and what we’re doing at Salience Labs is co-opting those components that already exist to build a photonic processor.”
Salience Labs will innovate on both the photonics and electronics side. On the photonics side, the company will build on work done by Salience co-founder Johannes Feldmann during his PhD. He built a prototype photonic computing chip which encodes data using the amplitude of light and then modulates that light to perform matrix multiplication at extremely high speeds. The compute element uses an electro-optic modulator, applying a voltage to the waveguide to modulate the light.
Compared to other approaches based on optical phase, coherent light isn’t required for Salience’s amplitude-based approach, and there are no interferometers, making the architecture simpler, Feldmann told EE Times. Until recently, this amplitude-based approach was based on components it wasn’t possible to fabricate in a foundry, but that has changed, said Kewada.
“At the point in time when [other photonic computing companies] were established, one would have looked at the amplitude-based approach and thought, that’s great, but you can’t fabricate that in a foundry,” she said. “One of the things we’ve done at Salience is move towards completely foundry-based components, and that step happened after everyone else was established.”
The benefits of Salience’s amplitude-based approach include the ability to clock the chip at tens of gigahertz, and the ability to easily perform multiple computations simultaneously using different wavelengths of light (up to 64 vectors can be stacked using this technique). The result, said Kewada, is very high bandwidth compute suitable for AI acceleration at low latency.
A paper on Feldmann’s prototype chip, published in Nature, describes how the prototype chip was used to run convolutional neural networks for image recognition, demonstrating matrix multiplication at up to 13 GHz, and multiplexing with four simultaneous wavelengths of light.
Salience is also working on a partner electronic ASIC for data orchestration. The ASIC chiplet has a highly distributed memory architecture that allows data to be pumped into the photonics chiplet, keeping it highly utilized.
“How to feed a chip that clocks much faster than the electronics is a core part of our innovation,” Kewada said. “It relates to how we stack our photonic chip over our memory in a sort of on-memory compute architecture.”
Salience’s photonic chiplet will be stacked on top of its electronic one, keeping the chiplets as close to each other as possible using existing packaging technologies, most likely an interposer-based solution, Kewada said.
Salience Labs is up against more established startups including Lightmatter and Lightelligence in this space. Kewada said there was more than enough room for multiple photonic computing architectures to co-exist.
“In the future, there’s going to be quite a significant amount of compute workloads in quite a large amount of segmentation, and huge amounts of different hardware that’s going to be targeting those different use cases,” she said. “At Salience, we’re focusing on where it is that our technology really shines – the use cases we know we can add value to.”
The hybrid Salience chip will initially target inference workloads (though training workloads are possible, Kewada said), especially those that can take advantage of the design’s low latency. This includes AI-based communications signal processing in 5G basestations, robotics, vision systems and more.
“We have a lot of faith in our photonic approach, which gives us a significant throughput of compute, and enables us to continue to scale,” she said. “The beauty of a hybrid photonic-electronic approach is that you can scale it, and go far beyond [our current prototype] in a way electronic architectures can’t.”
Salience’s seed funding round was led by Cambridge Innovation Capital and Oxford Sciences Enterprises, with Oxford Investment Consultants, former Dialog Semiconductor CEO Jalal Bagherli, ex-Temasek Board Member Yew Lin Goh and Arm-backed Deeptech Labs participating.
Salience Labs has around 10 employees today, most of whom are in the UK, and the company aims to grow its headcount to around 15 by the end of the year.