Designed to address the limitations of Moore’s law 2D scaling, Applied Materials’ latest portfolio of 3D gate–all–around (GAA) transistor technologies and extreme ultraviolet (EUV) lithography solutions aims to provide improved power, performance, area, cost, and time to market — otherwise known as PPACt — for chipmakers eager to extend 2D scaling with EUV.
In an EE Times Special Project, More than Moore, Nirmalya Maity, corporate vice president of Advanced Packaging at Applied Materials, explained that the need for innovations in the semiconductor industry continues to grow, especially as time to market for newer chip generations slows and costs increase.
Maity said in a blog post, “The internet of things, big data, and artificial intelligence are fueling a new wave of growth for the semiconductor industry. But while the need for chip innovation has never been greater, classic Moore’s law 2D scaling is slowing. Chip shrinks are taking longer and costing more with each successive generation. This is prompting the need for new design and manufacturing paradigms as chipmakers and system companies seek to continue driving improvements.”
This is where Applied Materials believes its latest technologies for 3D GAA transistor manufacturing and advanced patterning films for EUV can fill the gap of classic Moore’s law scaling.
Enhanced patterning films for EUV
Applied Materials’ Stensar Advanced Patterning Film for EUV, one of seven solutions announced last week (Apr. 21), allows chipmakers to modify EUV hardmask layer thickness and etch resiliency to “achieve near–perfect EUV pattern transfer uniformity across the entire wafer,” according to the company. This is achieved with the company’s chemical vapor deposition system.
According to the company in its press release, “The emergence of EUV lithography has enabled chipmakers to produce smaller features and increase transistor density. However, the industry has reached a point where further scaling with EUV is introducing challenges that require new approaches to deposition, etch, and metrology.”
The company also highlighted its Sym3 Y etch system and PROVision eBeam metrology technology to improve EUV patterns. The Sym3 Y etch system consists of multiple high–conductance chambers capable of etching and depositing specific materials before etching them on a wafer. This can help mitigate stochastic errors, which in turn improves both yields as well as the power and performance of a chip.
Meanwhile, the company claims its PROVision eBeam solution will enable chipmakers to view multilayer chips with nanometer resolution, high speed, and through–layer imaging. Paired with its Elluminator technology, Applied Materials says its eBeam portfolio can enable imaging at 1–nm resolution at a rate of 10 million measurements an hour and will allow chipmakers to capture 95% of back–scattered electrons for a deeper look at chip dimensions and edge placements.
Improving 3D GAA transistors
Applied Materials also unveiled two new iterations of its Integrated Materials Solution (IMS) designed to improve GAA transistor channels and metal gate stacks, which the company claims can help achieve higher drive currents and transistor performance.
The company originally designed its IMS system to use critical process steps within a vacuum to enable a higher level of interface engineering and tuning, which, according to Uday Mitra, vice president of Engineering at Applied Materials, can provide equivalent oxide thickness scaling that improves drive current by 8% to 10%.
Applied Materials’ latest instance of its IMS, however, addresses specific complications when modifying gate oxide stacks.
“A major challenge of manufacturing GAA transistors is that the space between the channels is only around 10 nm, and customers must deposit the multilayer gate oxide and metal gate stacks around all four sides of the channels in the minute space available,” Applied Materials said. “A thinner gate oxide results in higher drive current and transistor performance. However, thinner gate oxides typically result in higher leakage current that wastes power and creates heat.”
To alleviate this issue, Applied Materials incorporated atomic layer deposition, thermal steps, plasma treatment steps, and metrology — all of which is executed within a vacuum system — to produce thinner GAA transistor gate oxides by 1.5 angstroms while also reducing gate leakage by more than 10×, according to the company.
Applied Materials has also designed an IMS system capable of tuning transistor threshold voltages to help computing applications meet specific performance–per–watt goals, such as high–performance servers.