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EETimes – A Post-Moore’s Law World

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Even in a post–Moore’s law world, semiconductor technology continues to advance, seeking to yield improvements and pivoting into new technical directions, such as the advanced packaging of multiple heterogenous integrated semiconductor dies, or chiplets. The result is new manufacturing processes that add complexity and defectivity — making test a key component for success.

Advanced packaging continues the benefits of Moore’s Law in ways other than just scaling fab process nodes. Disaggregating functions, the opposite of the monolithic SoC approach, allows for focusing advanced fab process design on just the core compute and accelerators, thus saving design effort and cost by not changing other functions.

Moore’s Law 2D scaling is stalling. With each successive iteration, chip shrinking takes longer and costs more. As a result, new design and production paradigms are required. Meanwhile, silicon photonics is evolving from a technology reserved for niche markets to an accessible technology for higher–volume markets. We examine the promise and pitfalls in our upcoming More than Moore Special Project.

The present-day focus is “optimization per use case” enabled by the flexibility to more easily choose functions to include in the packaged device. The result continues to deliver the performance and power wins previously seen with Moore’s Law.

This new approach brings additional test challenges, and test is vital for success and economic viability. For example, known good die (KGD) is a significantly higher priority now, along with the related technical challenges of wafer probe, including density, signal count, signal integrity, and especially cost. Going forward, there will be additional challenges and a focus on the importance of testing inter–die interactions from package test to system/functional test.

Some of the test cost challenges will include expensive and fragile high–end probe cards, and more of them, for more unique die tested at wafer. This motivates a focus on reducing cost, for example, by increasing multi–site and related tester efficiency. Considerations of adding more test coverage need to balance test cost with coverage and quality — from wafer to system level test. A desire for more test data in less time is driving multiple new high–speed DFT approaches, including Streaming Scan Networks (SSN) and high–speed protocol–based test.

A semi–log plot of transistor counts for microprocessors against dates of introduction, nearly doubling every two years. (Source: Max Roser, Hannah Ritchie – Wikipedia) (Click image to enlarge)

In a post–Moore’s Law world there will be lots of unknowns. Will the benefits of chiplets be realized? How will new die interface standards evolve? Test program and result data sharing are key to making this work.

Other questions will continue to emerge, such as when will advanced packaging be fully commonplace and economical enough to expand into more device segments; or can data analytics and disparate sources of data be tamed to meaningfully address anticipated design, manufacturing, and test challenges? The answers to all of these questions will have a significant bearing on how the post–Moore’s Law world evolves.

Ed Seng is the strategic marketing manager for Advanced Digital at Teradyne


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