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As Classic Moore’s Law Dims, Heterogeneous Integration Steps Into the Limelight

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The internet of things, big data, and artificial intelligence (AI) are fueling a new wave of growth for the semiconductor industry. But while the need for chip innovation has never been greater, classic Moore’s Law 2D scaling is slowing.

Chip shrinks are taking longer and costing more with each successive generation. This is prompting the need for new design and manufacturing paradigms as chipmakers and system companies seek to continue driving improvements in power efficiency, performance, area, cost, and time to market — which Applied Materials calls PPACt.

Packaging shakes off a commodity reputation

Nirmalya Maity

For decades, semiconductor PPACt roadmaps were achieved through 2D planar shrinking and monolithic semiconductor integration, which proceeded with metronomic precision. During that time, semiconductor packaging was often regarded as a low–value, commodity part of the industry. Its primary function was to protect the die and connect it to the printed circuit board (PCB), which routed power and signals between chips and modules.

As computing has evolved from PCs to mobile devices and now the AI era, the role of packaging has changed dramatically. Today, advanced packaging enables heterogeneous design and integration, which provides an alternative way to continue the PPACt benefits associated with traditional Moore’s Law 2D scaling. The world’s leading chip and system companies are adopting this new approach to Moore’s Law as a competitive imperative.

Heterogeneous approaches allow engineers to disaggregate a large design into smaller chiplets that can be connected in a single package to deliver PPACt improvements. One approach to bring chiplets together is through 3D stacking using through–silicon vias (TSVs). 3D interconnects similar to TSVs can be much shorter than conventional wiring, enabling lower power consumption and higher I/O density.

Moore’s Law 2D scaling is stalling. With each successive iteration, chip shrinking takes longer and costs more. As a result, new design and production paradigms are required. Meanwhile, silicon photonics is evolving from a technology reserved for niche markets to an accessible technology for higher–volume markets. We examine the promise and pitfalls in our upcoming More than Moore Special Project.

For example, compared with conventional bump–to–PCB connections, TSVs can increase I/O density by approximately 100× and reduce energy–per–bit transfer by approximately 15× depending on architecture and workload, thus enabling power–efficient 3D die stacking. Performance can also be increased as logic and memory are brought into closer proximity.

Cost is reduced in two ways: Smaller dies typically have higher yields and leading–edge node wafers are generally more expensive than wafers based on previous nodes, meaning engineers can mix and match performance–critical dies with other chiplets. This results in a lower blended cost. Time to market can also be reduced as proven IP chiplets are incorporated more quickly.

Heterogeneous design and advanced packaging enable PPACt scaling in multiple ways. (Source: Applied Materials) (Click image to enlarge)

Hybrid bonding is waiting in the wings

The next revolution in advanced packaging is hybrid bonding. It provides a major improvement over conventional multi–chip packaging techniques, whereby I/O pins are connected to a substrate using metal bumps, with the substrate’s wiring used to complete the electrical interconnections between chips. Hybrid bonding connects chips and wafers with direct copper–to–copper bonding, which reduces wiring distances and further increases I/O density to improve power efficiency and system performance. Compared with TSVs, hybrid bonding will enable another 10× increase in I/O density and another 2× improvement in energy per bit.

Hybrid bonding is the next innovation on the packaging system interconnect roadmap. Each successive technology offers higher input–output density, as well as lower power consumption per bit of data transfer. (Source: Applied Materials) (Click image to enlarge)

Enabling hybrid bonding requires a broad suite of advanced semiconductor manufacturing technologies. To achieve the best performance, key technologies for bond–pad formation, planarization, surface preparation, and bonding must be co–optimized.

Heterogeneous design and advanced packaging techniques such as hybrid bonding will be increasingly critical for the world’s leading semiconductor and system companies. Applied Materials is helping to accelerate the trend through the unique breadth and depth of our portfolio. We combine these at the world’s most advanced packaging lab in Singapore, where we collaborate with customers and industry partners who enable us to demonstrate a complete and proven suite of manufacturing technologies for die–to–wafer and wafer–to–wafer hybrid bonding. Our intent with these engagements is to build an advanced packaging ecosystem that can accelerate our customers’ PPACt roadmaps and overcome the slowing of classic Moore’s Law scaling.

Packaging and localization

Pandemic–driven supply chain shortages have caused economic disruptions to major industries, with automobiles as one prominent example. Manufacturers and even nations are rethinking semiconductor sourcing strategies, and this extends to packaging.

According to a November 2021 report by trade group IPC and research firm TechSearch International, North America accounts for only 3% of global advanced semiconductor packaging production. This deficit may be addressed by the $52 billion U.S. CHIPS Act passed by Congress last year. The bill calls for the creation of a domestic National Advanced Packaging Manufacturing Program, a move supported by U.S. semiconductor industry leaders including Applied Materials.

—Nirmalya Maity is corporate vice president of Advanced Packaging at Applied Materials.

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