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120-GBd BERT validates 1.6T designs


The M8050A bit error ratio tester (BERT) from Keysight characterizes chip deployments up to 120 Gbaud for the 1.6T (1 trillion bits per second) market. It enables the design and characterization of receivers used in next-generation data center networks and server interfaces.

Engineers challenged with higher loss and distortion when moving from 112 Gbps per lane to 224 Gbps per lane can take advantage of the M8050A’s high signal integrity to obtain greater test margin. This allows customers to move to next-generation 1.6T designs, while maintaining the flexibility needed to adapt the M8050A to meet future requirements.

In addition to symbol rates from 2 GBd to 120 GBd, the M8050A supports non-return-to-zero (NRZ), PAM4, PAM6, and PAM8 line coding. The pattern generator BERT module comes in one-channel and two-channel versions occupying two and three slots, respectively, in an AXIe chassis. It pairs with a remote head and a clock module with jitter modulation. An Infiniium 80-GHz UXR oscilloscope serves as acquisition-based error analyzer. Together, these instruments form a comprehensive 1.6T receiver and transmitter test platform.

M8050A BERT product page

Keysight Technologies  

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