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RTL Design Engineer At Moschip In Bengaluru


EXPERIENCE: 3-15 years

General knowledge how things work in RTL team and be able to handle basic-to-mid level

RTL tasks

  • RTL design/release flows/infra (LINT, CDC, UPF, IPXACT, CSR …)
  • Good working knowledge in general scripting (Perl, Python, Make …)
  • Customer methodology/flow ask and complaints. Should be able to take up infra cleanup.

Some good examples of infra cleanup

  • Correctly clean PERL warnings during RTL build to find/fix any poor usage of variables
  • Own automated tools driven regressions runs of available tools in alternate modes for RTL-focused builds
  • VCS compiles with selective, not global-ignore, lint and warning bars on just ckt models, hardIP blocks stand-alone, full RTL-only PHY
  • Cleanup of grep or other bars to prevent bad `ifdef usage, naming conventions (extend spyglass or add our own), etc.
  • Creating design build configurations for different modes like ATPG, HWEMUL





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