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Patent Trends Foretell Chipmakers’ Fortunes

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Building out a patent portfolio is a tried-and-true path toward success, but it’s no guarantee. Sheer numbers are one thing; but the quality of the patents a company applies for and receives can be just as important, if not more so. So which semiconductor companies are building patent portfolios wisely, and which ones seem to be amassing patents simply for the sake of doing it?

In January, LexisNexis published its “Innovation Momentum 2022: The Global Top 100” list in which the dynamics of innovative strength over the last two years were analyzed across industries to pinpoint technology owners who outperform their peers. The report uses a new approach that focuses on recent innovations rather than giving full weight to patents nearly 20 years old.

The semiconductor industry is one of three industries analyzed in the report, and most of the semiconductor companies among the top 100 are related to semiconductor device manufacturing, be it as an integrated device manufacturer (IDM), a foundry, or an equipment manufacturer. With interest sparked by the Innovation Momentum report, we took a closer look at the patent classifications of the semiconductor companies in the top 100.

By analyzing the respective Cooperative Patent Classification (CPC) classes at a general level, we identified the ten most frequent classifications including typical classifications for semiconductor device manufacturing (H01L 21/00, H01L 27/00, H01L 29/00) and those characteristic of semiconductor packaging (H01L 23/00, H01L 24/00, H01L 25/00). This preliminary view prompted the question: how have semiconductor device manufacturing and packaging — particularly advanced packaging — evolved, and what is the status of advanced packaging from a patent portfolio perspective?

Using combinations of classifications and keywords to discover related patents, the development of manufacturing, packaging, and advanced packaging can be traced over time. Charting this, we can see the development of the three technology fields since 2010. Even if the absolute number for device manufacturing is much larger than for advanced packaging, the latter accelerated quickly with the number of active patent families for advanced packaging increasing by a factor of 1.6 between 2010 and 2021.

The top 10 advanced packaging companies ranked by patent portfolio strength (Patent Asset Index) are no surprise. The chart shows for the last three years the average patent quality (Competitive Impact) versus the portfolio size; while the bubble size represents the strength of the advanced packaging portfolio (Patent Asset Index). TSMC has the largest and strongest portfolio in all three years, followed by Samsung, and Intel. Typically, the average patent quality decreases as the portfolio size increases as found for ASE, Intel, Micron, and Qualcomm, which demonstrates an unfavorable Innovation Momentum. In contrast, TSMC and Samsung are maintaining or even increasing the average patent quality which is characteristic for a positive Innovation Momentum. The second characteristic portfolio development for a positive Innovation Momentum is found for Infineon: Infineon scaled back its advanced packaging portfolio, but thereby improved its average patent quality.

As the portfolio strength has evolved for the top three advanced packaging companies, we can see a corresponding increase in the rollout of new packaging technologies: In the preceding decade, these companies introduced or announced chip on wafer on substrate (CoWoS); hybrid memory cube (HMC); high bandwidth memory (HBM), integrated fan-out (InFO); fan-out panel level packaging (FO-PLP); embedded multi-die interconnect bridge (EMIB); system on integrated chiplets (SoIC); X-Cube and I-Cube4; Foveros; omni-directional interconnect (ODI); and Co-EMIB.

Back in 2010 Intel and TSMC had about the same portfolio strength for their advanced packaging patents, while Samsung was ahead of both. Whereas TSMC has been on a steady upward trend, Samsung lagged by a couple of years until it kicked development into gear about five years ago. Intel was less active, and now its advanced packaging portfolio strength appears to be flattening. Outwardly, Intel holds to the concept of leading the technology offering both at the foundry and the assembly plant.

That said, Intel’s direction and mantra may still fit with the advanced packaging directions in the wider industry. There is a great deal of overlap in development efforts amongst the three that we have identified as the leaders, but each has a unique approach which is either a more focused technology direction or a willingness to cover all bases.

It’s an oversimplification of extreme proportion, but we could think of semiconductor products in one of two categories. On the one hand, there is high-performance computing. For the sake of discussing advanced packaging, let’s put everything from AI to desktop computers chips in there. On the other hand, there are extremely high-volume devices for mobile and IoT applications.

Intel is well known for making microprocessors. It may come as no surprise that much of its product development has revolved around the technology needed to build each new generation of server and personal computer device. We can see that echoed in its directions for advanced packaging as well.

Intel packaging is most well-known for EMIB and Foveros. Although these techniques are meant to provide some cost relief in production along with performance enhancement, the focus is definitely high-performance computing.

Intel Embedded Multi-die Interconnect Bridge (EMIB) (source: Intel)

This is not to suggest that there is any disconnect with Intel’s product strategy. This is certainly a time of expanded computing power in server farms requiring a lot of top end horsepower. But Intel has said it intends to address foundry clients as well as contract packaging. There could be more to the Intel roadmap than we are privy to, but the technology development made public appears to target large, fixed, high performance computing.

The Intel advanced packaging technology focus is a better fit to address HPC. This is also true from the point of view of the relative cost of the EMIB and Foveros assembly systems. For Intel branded products, the assumption is that this fits with the roadmap and product mix. For contract clients, we may speculate that the focus could be on the US military.

On the other hand, we have Samsung targeting the highest volume of assembly possible for microelectronics products with their panel level packaging. Samsung have truly embraced the more than Moore approach to continuing the economics that created the juggernaut known as the semiconductor industry.

Samsung Galaxy Smartwatch with FO-PLP Exynos 9110 (source: SystemPlus Consulting)

Samsung places an emphasis on devices such as the Exynos for the smartwatch. The Galaxy Watch debuted in August of 2018 powered by the Exynos 9110 assembled on the fan-out panel level packaging (FO-PLP) platform and integrating an application processor and power management IC (PMIC) in the same package.

In the last example, there is TSMC, long the world’s leading semiconductor foundry. Many years ago, TSMC realized that staying at the forefront of technology would require more than innovation at the silicon wafer level. Staying on the curve meant co-design and optimization between the chip and its final assembly and the world’s biggest foundry began its push into packaging.

An examination of the advanced packaging direction for TSMC may lead you to believe there is no direction. In our estimation, the TSMC suite of packaging services attempts to capture all the current and future trends. TSMC covers the gamut from very high volume and lower cost products to the cutting edge of high-performance computing.

Weighing the relative merits of business approaches between foundry and IDM are beyond the scope of this post (and well beyond our pay grades). But an old debate between the integrated device manufacturer and fabless will be interesting to watch in the coming years. In the beginning, the fabless approach was all about shedding costs and conventional Moore’s Law. Now with high-performance computing depending increasingly on advanced packaging, the IDM versus fabless approach is once again front and center.

TSMC integrated fan-out (InFO) package used for Apple A-series application processors (source: SystemPlus Consulting)

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