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How can 3D FeFETs substitute NAND flash for low-latency storage


The part 1 of this two-article series outlined the NAND flash technology and how it transitioned from 2D to 3D NAND flash. The article also explained the current challenges in the way of density scaling for higher capacity storage applications. Now, part 2 explains how non-volatile memory technology is emerging to cater to a variety of storage applications.

Relying on a long track record in 2D and 3D NAND flash technology development, part of imec’s storage R&D activities focus on continuing the conventional GAA 3D NAND flash scaling roadmap. By both modeling and experiments, the research team explores innovations in elementary 3D-NAND cells to allow for a further reduction in x-y-z dimensions.

With the modeling and simulation work, researchers investigate the impact of introducing new materials and architectures on the electrical performance of the NAND flash memory cells. Modeling also allows the team to enhance fundamental understanding, and to identify and mitigate 3D NAND flash cell scaling roadblocks. The experimental work is structured around a test vehicle with a limited number of layers—typically three to five, 300 nm in height—that are relevant for studying the effects of scaling on the electrical memory cell metrics.

A view on recent insights and achievements

A z-shrink of the NAND flash layer stack involves squeezing the materials that are used for creating the word-line layers, including the word-line metal. Currently, vertical word-line pitches in commercial 3D NAND products range between 50 nm and 60 nm, with tungsten (W) being the word-line metal of choice. It also acts as a gate electrode for the NAND flash memory cell and is integrated in the stack by a replacement metal gate process.

Reducing the word-line metal thickness comes along with an unwanted resistivity increase, which enhances resistance-capacitance (RC) delay and slows down access times. Imec, therefore, is looking at alternative metals such as Ru and (barrierless) Mo with potentially lower resistivity at small dimensions. At the 2021 IEEE Symposium on VLSI Technology and Circuits (VLSI 2021), imec’s team demonstrated improved resistivity and memory characteristics for Ru and Mo word lines down to a record low 40 nm word-line pitch.

Figure 1 A cross-section of Mo is integrated into a 5-stack 3D NAND with scaled word lines down to 40 nm pitch. Source: imec

The team is also exploring alternative materials for the charge trap layers, the tunnel dielectrics and the metal gate stack, and is investigating their impact on memory performance. For example, engineers investigated how high-work-function metals in combination with a thin high-k liner can improve the 3D NAND erase operation.

In today’s GAA 3D NAND flash structures, the channel material used is polysilicon. Depositing the polysilicon material in the ‘plug’ that runs through the material stack is considered the most cost-effective way to fabricate the devices. But as the number of layers increases, the inherently defect-rich polysilicon channel deteriorates the device read current.

Imec, therefore, explores ways to improve channel mobility by either introducing alternative channel materials or improving the quality of the polysilicon channel. At the 2021 IEEE International Electron Devices Meeting (IEDM 2021), imec’s team presented the results of using metal-induced lateral crystallization (MILC) in a 3D test structure to boost the polysilicon channel quality. MILC is a process in which amorphous silicon transforms into a crystalline state at relatively low temperatures, catalyzed by the presence of a metal such as Ni. They concluded that it’s possible to achieve up to 10 times higher mobility and enhanced channel control with an improved MILC process compared to a regular polysilicon channel.

Modeling work focuses, for example, on understanding the non-ideal programming efficiency of charge trap layer flash memories. This inefficiency, which is reflected in the slope of the incremental step pulse programming (ISPP) curve, results in a higher programming voltage. The team recently gained a better understanding of this poorly understood phenomenon. At IEDM 2021, researchers outlined different contributions to the ISPP slope and proposed ways for mitigation, for example, by using a high-k dielectric within the charge trap layer cell.

Figure 2 Contribution of carrier injection (inj), escape (esc) factors and trap filling on ISPP curve are shown on the top and slope at the bottom. Source: imec

Other modeling work focuses on the impact of introducing new materials and architectures—such as the trench cell—on the mechanical stress within the layer stack. Mechanical stress is known to introduce wafer warpage, local pattern deformation, and cracks within the 3D NAND flash structure. At the 2021 IEEE International Interconnect Technology Conference (IITC 2021), imec presented a finite-element modeling (FEM) approach that can be used to evaluate and mitigate wafer warpage in future 3D NAND memory fabrication without needing to experimentally build a >100-layer stack.

NAND flash tapping into new market segments

Today, 3D NAND flash technology is used in high-density, low-cost data-heavy storage applications such as solid-state drives. But the technology is increasingly finding its way into other market segments, particularly the low(er)-latency storage segment. Here, it can potentially serve a range of storage applications that require faster read access time than traditional NAND flash for applications such as look-up tables for databases. This faster variant of NAND flash will enter the storage class memory (SCM) space, which should help close the gap between fast, volatile DRAM and slow, non-volatile 3D-NAND flash.

Low-latency storage applications will require shorter read access times than conventional high-density 3D NAND flash. Several routes are available to make that possible. One way is to revert to single bit memory cells. This mainly improves program speed to ~30 us to approach read speed of ~10 us. Further optimizations of the design space may involve reducing the word-line lengths or altering the RC-delay parameters. With these and other measures, NAND flash technology is expected to enter the low-latency storage market with read access times in the order of 10 µs.

Low-latency storage: a major role for FeFET

In the longer term, much is expected from ferroelectric memories to fulfill this role, more particularly from memories based on the 3D ferroelectric field effect transistor (3D FeFET). 3D FeFETs are expected to outperform 3D NAND flash in terms of speed, making them ideal candidates for low-latency storage.

Figure 3 Here is an imec view of the data storage roadmap. Source: imec

The architecture of an FeFET is similar to that of a traditional n-channel MOS transistor, in which the gate dielectric has been replaced by a ferroelectric material such as HfO2 in its orthorhombic crystal phase. A ferroelectric comes in two electrical polarization states, which can be reversed with an external electric field by applying a pulse to the transistor gate. After the field is removed, they retain their polarization state, giving the material its non-volatile characteristic.

The two stable, remnant polarization states of the gate insulator modify the transistor threshold voltage. The binary states are thus encoded in the threshold voltage of the transistor. Here, the operating principle of an FeFET memory is very similar to that of NAND flash: writing of the memory cell is completed by applying a pulse to the transistor gate, and reading is performed by measuring the drain current.

Just like NAND flash, FeFETs can be fabricated in a true 3D fashion by using a 3D NAND-like manufacturing flow. To build 3D FeFETs, a trench-like architecture is preferred over a GAA-structure, as FeFETs don’t benefit from circular charge carrier injection.

Although still in the early stage of R&D, 3D FeFETs are expected to present some notable advantages compared to 3D NAND technology. They are simpler to process, consume less power, and can potentially operate at much lower voltage, which benefits their reliability. Additionally, read and write access times in the order of a few µs are feasible, making them an attractive alternative to 3D NAND for future low-latency applications.

Optimizing 3D FeFETs for low-latency storage

Imec is addressing the main challenges related to the processing, characterization, and reliability of 3D FeFETs. Researchers are exploring the best possible architecture, material combinations, and memory operating mechanisms such as program/erase scheme to optimize 3D FeFETs for low-latency storage applications.

To enter the NAND side of the storage class memry space, speed and cycling endurance or the number of program/erase cycles before failure are the most crucial parameters. While the cycling endurance of 3D NAND is limited to about 105, the imec team is working toward 107 cycling endurance for 3D FeFET. This could already be demonstrated for planar FeFET architectures. A higher cycling endurance is expected to come along with a slight penalty in density and retention.

One approach for improving cycling and speed is optimizing the channel material. Just like in NAND, the FeFET channel today is composed of polysilicon. But this material challenges FeFET operation. The combination with the ferroelectric HfO2 stimulates regrowth of an interfacial oxide layer, which creates unwanted trapping effects for the charge carriers. That, in turn, degrades the program/erase cycling performance of the memory. Besides looking into mitigation strategies, imec explores alternative channel materials, including oxide semiconductors. These channel materials should come with a low thermal budget to preserve the orthorhombic phase of the HfO2 or other ferroelectric layers.

Figure 4 Memory window after applying 100-ns program/erase pulses is shown on the top, while the evolution of the threshold voltage VT with cycling after the program and erase is displayed at the bottom. Source: imec

The orthorhombic crystal phase of HfO2 can be stabilized by using an optimal combination of dopants, strain, and annealing. Today, mainly silicon is used as a dopant atom, as it can keep the orthorhombic phase even at higher thermal budgets. The imec team is also studying alternative dopants and doping conditions while exploring other ferroelectric materials besides HfO2.

For the architecture, imec actively pursues the 3D trench architecture, of which a first test vehicle has been demonstrated.

For decades, NAND flash was aimed at high density storage applications. Now, we see faster variants aimed at low-latency storage. For the latter application, imec sees an important role for 3D FeFET in the future. For both NAND and FeFET, imec explores novel materials and cell architectures, and studies their impact on memory performance.

Besides, researchers are gaining more insight into the main reliability degradation mechanisms. While innovations in 3D NAND flash aim at the continuation of the high-density storage roadmap, imec prepares 3D FeFET for its future role in the low-latency storage market.

Maarten Rosmeulen is program director of the Storage Memory program at imec.

Jan Van Houdt is program director for ferroelectrics at imec and professor at the Physics and Astronomy department of the KU Leuven.

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